CMOS AND Gate Design Project
EE 307-01 Winter 2008
Group 7
http://0107ee307w08.pbwiki.com
Chris Herrinton - cherrinton@gmail.com
Alvin Hilario - alvin.hilario@gmail.com
Dan Ford - daniel.ford@gmail.com
Introduction
Designing an 8-input AND gate presents numerous ways to realize the gate to meet requirements and increase performance. This project first analyzes three default AND gates for their figure of merit and then designs a custom fourth AND gate that improves upon the previous designs. The figure of merit defines the overall performance of the gate and is based on the propagation delay in nanoseconds, the power dissipation in milliwatts and the transistor area in square micrometers, with each critereon weighted equally. Our goal was to design an optimized AND gate that resulted in the lowest possible figure of merit while maintaining noise margins of 0.25V, a maximum of 250 square microns of total transistor area, and a minimum feature size of 0.25 microns for each transistor
Summary of Results
Gate |
Delay (ns) |
Power (mW) |
Area (um^2) |
Figure of Merit |
Big Two-Level AND |
1.43 |
0.7986 |
34.5 |
39.40 |
Medium Two-Level AND |
1.26 |
0.7072 |
13.5 |
12.02 |
Four-Level AND |
0.796 |
1.166 |
38.5 |
35.76 |
Optimized AND (based on big two-level AND) |
1.51 |
0.6557 |
4.75 |
4.701 |
Transistor Sizing
- Big Two-Level AND
- MP1-8 W=0.25um L=0.25um
- MN1-8 W=16um L=0.25um
- MP9 and MN9 W=4um L=0.25um
- Medium Two-Level AND
- NAND4
- NMOS: W = 4um L = 0.25um
- PMOS: W = 0.25um L = 0.25um
- NOR2x4
- NMOS: W = 2um L = 0.25um
- PMOS: W = 8um L = 0.25um
- Four-Level AND
- NAND2
- NMOS W = 1um L = 0.25um
- PMOS W = 0.25um L = 0.25um
- NOR2x4
- NMOS W = 2um L = 0.25um
- PMOS W = 8um L = 0.25um
- NAND2x16
- NMOS W = 16um L = 0.25um
- PMOS W = 4um L = 0.25um
- Inverter
- NMOS W = 32um L = 0.25um
- PMOS W = 23um L = 0.25um
- Optimized AND
- MN1 W=.25u L=0.25u MN2 W=.5u L=0.25u MN3 W=.75u L=0.25u MN4 W=1u L=0.25u MN5 W=1.25u L=0.25u MN6 W=1.5u L=0.25u MN7 W=1.75u L=0.25u MN8 W=2u L=0.25u
- MP1-8 W=.25u L=.25u
- MN9 and MP9 W=4u L=.25u
Optimized AND Gate Circuit Schematic
MN1 W=.25u L=0.25u MN2 W=.5u L=0.25u MN3 W=.75u L=0.25u MN4 W=1u L=0.25u MN5 W=1.25u L=0.25u MN6 W=1.5u L=0.25u MN7 W=1.75u L=0.25u MN8 W=2u L=0.25u
MP1-8 W=.25u L=.25u
MN9 and MP9 W=4u L=.25u
Figure of Merit Analysis
Big Two-Level AND
Area:
8 NMOS W=.25u L=.25u
8 PMOS W=16u L=.25u
1 NMOS W=4u L=.25u
1 PMOS W=4u L=.25u
Area = 8*(.25u)(.25u) + 8*(16u)(.25u) + 1*(4u)(.25u) + 1(4u)(.25u) = 34.5u^2
Figure of Merit = 1.42982 ns * .79859390mW * 34.5u^2 = 39.39367572
Of the three originally specified AND gates, the Big Two-Level AND gate being the simplest in design, performed the worst. It clocked in slowest at 1.42 ns and sized almost the largest at 34.5 um^2. Having small size pull-up PMOS transistors allows very little current, giving it its only positive, little power dissipation. Leaving a lot of room for improving in terms of design, this gate became the obvious choice as a model for our custom AND gate.
Medium Two-Level AND
Delay: 1.25663ns
Average Power Dissipation: 707.20785uW
Area: 13.5um^2
Figure of Merit: 12.02
This gate actually performed the best out of any of the 3 given AND gates, although not by much. The main difference between this gate and the others with respect to the Figure of Merit calculation is the total size of the gate - only 13.5um^2, compared with 35um^2 and 39um^2. Due to the favorable Figure of Merit (FOM) value for this gate, we originally selected this 2-level NAND/NOR layout as the base for our optimized AND gate. Although we were able to produce a gate with a FOM of around 6-7 (effectively halving the original FOM), we later found that the 1-level AND left more room for improvement and could produce an even smaller FOM.
Four-Level AND
Propagation Delay = 0.79641ns
Area:
4x NAND2 Area =2 * (0.25um^2 + 0.0625um^2) = 0.625um^2
2x NMOS W = 1um L = 0.25um Area =1um*0.25um= 0.25um^2
2x PMOS W = 0.25um L = 0.25um Area =0.25um*0.25um= 0.0625um^2
2x NOR2x4 Area =2 * (0.5um^2 + 2um^2) = 5um^2
2x NMOS W = 2um L = 0.25um Area =2um*0.25um= 0.5um^2
2x PMOS W = 8um L = 0.25um Area =8um*0.25um= 2um^2
1x NAND2x16 Area =2 * (4um^2 + 1um^2) = 10um^2
2x NMOS W = 16um L = 0.25um Area =16um*0.25um= 4um^2
2x PMOS W = 4um L = 0.25um Area =1um*0.25um=1um^2
1x Inverter Area = 2* 8um^2 = 16um^2
1x NMOS W = 32um L = 0.25um Area =32um*0.25um= 8um^2
1x PMOS W = 32um L = 0.25um Area =32um*0.25um=8um^2
Total Area = 4 * 0.625um^2 + 2 * 5um^2) + 10um^2 + 16um^2 = 38.5um^2
FOM = (delay in ns) * (power in mW) * (area in square microns)
= 0.79641 * 1.1663 * 38.5 = 35.76
With the all the inputs of the gate tied together, this AND gate proved to have the best propagation delay performance, but less than mediocre power dissipation and total transistor area. The number and large size of these transistors attributes these performance characteristics. At each following level, the transistors progressively increase in size to rectify any skew from the output of the previous gate. Although this feature although maintains a small propagation delay, it increases power dissipation and total transistor size. The final inverter’s main role in the circuit provides a specified noise margin, and since the noise margin is less than perfect, it would be in the best interest of the figure of merit to have the inverter scaled down. This also remains true for the other transistors, that they must be scaled down to the point that they have a minimal effect of the propagation delay and a drastic effect on the power dissipation and total transistor size.
Optimized Two-Level AND
Size:
.25*.25*8+.25*.25+.5*.25+.75*.25+1*.25+1.25*.25+1.5*.25+1.75*.25+2*.25+2*4*.25 = 4.75um^2
Figure of Merit:
Prop Delay(ns) * Power Dissipation(mW) * Size in um^2 =
1.50938 * .65570479mW * 4.75um^2 = 4.701 ns*mW*um^2
Voh: 2.463 V
Vil:1.5868 V
Vol:0 V
Vih:1.697 V
NMH:Voh-Vih=2.463-1.697= .766 V > .25 V
NML:Vil-Vol=1.5868 - 0 = 1.5868 > .25 V
Design Decisions
After comparing the figure of merits for each of the three given gates it became evident that the transistor area influences the figure of merit the most. For the three examples, fast speeds came at the cost of high power dissipation and similarly low power resulted in a slower speed. The trade offs largely off set each other regardless of configurations with slower speeds around 1.2-1.5ns to go with low powers of around .700 mW, where as faster speeds of .8ns resulted in the power dissipation ballooning up to 1.200mW. Because of this, challenges arose while reducing size while keeping the speed and power approximately constant. Having the most room to improve in terms of area because of it's unnecessarily large W/L ratios on the NMOS's, we chose the Big Two-Level AND Gate. The PMOS W/L ratios remained constant for the test circuit to have the smallest transistor area, because they already reached the smallest feature size possible.
NMOS W/L sizing ratios became the basis of our reduction of transistor sizing plan. The NMOS W/L ratios gradually increase from MN8 to MN1 as per the suggestion of Mary Jane Irwin & Vijay Narayanan, CSE477 VLSI Digital Circuits Fall 2003, Lecture Slides. We originally designed the W/L ratios going from 1/1 to 16/1 doubling each time, with the exception of the MN3 : 8/1 MN2 : 12/1 transistors because of a desire to stay with 16/1 as our largest W/L ratio because of it's inclusion in the given design. This resulted in an across the board positive influence on all figure of merit aspects in the circuit. The speed benefited slightly dropping to 1.40ns, the power decreased to .750mW and the size obviously decreased as well. With encouraging results, and noting that speed and power became positively affected by this technique while size decreased, the we made the decision to take it further. The next custom AND gate designed featured linearly increasing W/L ratios instead of the previous exponential in order to further decrease the size. W/L's went from 1/1 to 8/1 with the widths increasing .25um per transistor. This would be our final custom AND gate that resulted in the overall best figure of merit. Though the speed of the transistor did not perform as well at 1.51ns, the power also went down to the lowest seen power of 0.655mW coupled with the smallest overall size resulted in our best figure of merit. Even though it clocks in slow, percentage wise the area of the transistor decreased so drastically that a 0.1ns change in speed did not affect it enough to prevent this model from being the overall winner.
Optimized AND Gate with 8-Bit Counter Input
PSPICE Code Modifications:
V1 Vin1 0 PULSE (0 2.5 0 0.5n 0.5n 5n 10n)
V2 Vin2 0 PULSE (0 2.5 0 0.5n 0.5n 10n 20n)
V3 Vin3 0 PULSE (0 2.5 0 0.5n 0.5n 20n 40n)
V4 Vin4 0 PULSE (0 2.5 0 0.5n 0.5n 40n 80n)
V5 Vin5 0 PULSE (0 2.5 0 0.5n 0.5n 80n 160n)
V6 Vin6 0 PULSE (0 2.5 0 0.5n 0.5n 160n 320n)
V7 Vin7 0 PULSE (0 2.5 0 0.5n 0.5n 320n 640n)
V8 Vin8 0 PULSE (0 2.5 0 0.5n 0.5n 640n 1280n)
MP1 Vdd Vin1 18 Vdd CMOSP W=0.25u L=0.25u
MP2 Vdd Vin2 18 Vdd CMOSP W=0.25u L=0.25u
MP3 Vdd Vin3 18 Vdd CMOSP W=0.25u L=0.25u
MP4 Vdd Vin4 18 Vdd CMOSP W=0.25u L=0.25u
MP5 Vdd Vin5 18 Vdd CMOSP W=0.25u L=0.25u
MP6 Vdd Vin6 18 Vdd CMOSP W=0.25u L=0.25u
MP7 Vdd Vin7 18 Vdd CMOSP W=0.25u L=0.25u
MP8 Vdd Vin8 18 Vdd CMOSP W=0.25u L=0.25u
MN8 18 Vin1 17 0 CMOSN W=.25u L=0.25u
MN7 17 Vin2 16 0 CMOSN W=.5u L=0.25u
MN6 16 Vin3 15 0 CMOSN W=.75u L=0.25u
MN5 15 Vin4 14 0 CMOSN W=1u L=0.25u
MN4 14 Vin5 13 0 CMOSN W=1.25u L=0.25u
MN3 13 Vin6 12 0 CMOSN W=1.5u L=0.25u
MN2 12 Vin7 11 0 CMOSN W=1.75u L=0.25u
MN1 11 Vin8 0 0 CMOSN W=2u L=0.25u
.TRAN 20n 5120n 0 10n
Average Power Dissipation
Average Power Dissipation = 9.8095 uW
This power dissipation is reasonable, because the output of the AND gate will only switch to high if all inputs are high. The ON time directly relates to the pulse width of the highest frequency input, five nanoseconds.
Appendix
The following links lead to the original test results for each of the circuits as well as their .cir files used to test them.
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